2/12/2023 0 Comments Bugzilla mrc![]() + arm_stack_protector_guard_offset = offs + error ("%qs is not a valid offset in %qs", str, + long offs = strtol (arm_stack_protector_guard_offset_str, &end, 0) + const char *str = arm_stack_protector_guard_offset_str + if (opts->x_arm_stack_protector_guard_offset_str) + error ("incompatible options %'-mstack-protector-guard=global%' and" + & opts->x_arm_stack_protector_guard_offset_str) + if (arm_stack_protector_guard = SSP_GLOBAL If (TARGET_THUMB2_P (opts->x_target_flags)) Static struct obstack -3157,6 +3160,26 arm_option_override_internal (struct gcc_options *opts, * Obstack for minipool constant handling. +#define TARGET_STACK_PROTECT_GUARD arm_stack_protect_guard #define TARGET_MD_ASM_ADJUST arm_md_asm_adjust +++ -829,6 +829,9 static const struct attribute_spec arm_attribute_table = ![]() + SSP_TLSREG, /* per-thread canary in TLS register */ĭiff -git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c +/* Where to get the canary for the stack protector. * config/arm/arm.opt (-mstack-protector-guard): Newĭiff -git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h (stack_protect_set): Adjust for SSP_GLOBAL. * config/arm/arm.md (reg_stack_protect_address): New. * config/arm/arm.c (arm_option_override_internal): HandleĪnd put in error checks for stack protector guard options. * config/arm/arm-opts.h (enum stack_protector_guard): New Of the process, permitting each process to use its own value for the Using the TLS register to index the stack canary helps with this, as itĪllows each CPU to context switch the TLS register along with the rest Running the same program concurrently: using a global variable for theĬanary in that context is problematic because it can never be rotated,Īnd so the OS is forced to use the same value as long as it remains up. SMP mode, where processes entering the kernel are essentially threads This is intended for the Linux kernel running in So that multiple threads running in the same address space can useĭistinct canary values. 10:23 implement TLS register based stack canary for ARM Ard 10:23 ` Ard Biesheuvelġ sibling, 0 replies 4+ messages in threadĪdd support for accessing the stack canary value via the TLS register, * Add support for TLS register based stack protector canary access type bar, args = 0, pretend = 0, frame = frame_needed = 0, uses_anonymous_args = 0 Return foo(_builtin_thread_pointer()) + 1 $ cat |arm-linux-gnueabihf-gcc -march=armv7-a -mstack-protector-guard=tls -mstack-protector-guard-offset=10 -mtp=cp15 -S -o -xc -fstack-protector-all -O3 Add support for TLS register based stack protector canary access Get spilled to begin with? How about a register that carries TLS+? Past: I suppose a register carrying the TLS register value will never The offset is always a distinct instruction.Īs for the spilling issues that have been fixed in this code in the Immediate offset field of the LDR instructions, so currently, the ADD of To modify the patterns so that the offset will be moved into the The patch is a bit rough around the edges, but produces the correct This means we can justĪdd an offset to TPIDRURO to obtain the address from which to load the Per-process metadata while running in the kernel. Which will start using the user space TLS register TPIDRURO to index This patch implements something similar, but for the 32-bit ARM kernel, The rest of the process, allowing each process to use its own unique This permits the kernel to use different memory addresses for the stackĬanary for each CPU, and context switch the chosen system register with Reason will do so on a call into the kernel, which means that there willĪlways be live kernel stack frames carrying copies of the canary takenĪArch64 implements -mstack-protector-guard=sysreg for this purpose, as ![]() Protector canary value is problematic on SMP systems, as we can neverĬhange it unless we reboot the system. This means that using a global variable for the stack In the Linux kernel, user processes calling into the kernel areĮssentially threads running in the same address space, of a program that Qing Zhao, Richard Sandiford, gcc-patches 16:34 ` implement TLS register based stack canary for ARM Ard BiesheuvelĠ siblings, 2 replies 4+ messages in threadįrom: Ard Biesheuvel 10:23 UTC ( / raw)Ĭc: keescook, Ard Biesheuvel, thomas.preudhomme, adhemerval.zanella, 10:23 ` Add support for TLS register based stack protector canary access Ard Biesheuvel Implement TLS register based stack canary for ARM public inbox for help / color / mirror / Atom feed * implement TLS register based stack canary for ARM 10:23 Ard Biesheuvel
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